Siva Kumar Sastry Hari

Sr. Research Scientist
Architecture Research Group
NVIDIA
Email: shari [at] nvidia [dot] com
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Siva Hari is a Senior Research Scientist in the Computer Architecture Research Group at NVIDIA. His research interests are in the fields of computer architecture, artificial intelligence, and systems. His current research focus is on making autonomous systems safe and HPC systems resilient via software and architecture level solutions. He obtained his Ph.D. and M.S. from the Computer Science Department at University of Illinois at Urbana-Champaign and Bachelor's degree from the Computer Science and Engineering Department at Indian Institute of Technology (IIT) Madras.

He received the 2014 David J. Kuck Outstanding Ph.D. Thesis Award from the Computer Science Department at the University of Illinois. He received the W.J. Poppelbaum Memorial Award from the Computer Science Department at the University of Illinois at Urbana-Champaign in 2012 for academic merit and creativity in computer hardware or architecture. He won the Margarida Jacome Best Poster Award at GSRC Annual Symposium, 2012. One of the papers he co-authored was selected for the IEEE Micro's Top Picks 2013, one was recognized as the Best Paper Award Runner-up at DSN 2018, and another received Best Research Paper Award at ISSRE 2020.




Conference and Journal Publications

arXiv and Workshop Publications

Patents

Theses

Software


Conference and Journal Publications

Top
  1. Generating and Characterizing Scenarios for Safety Testing of Autonomous Vehicles
    Z. Ghodsi, S. K. S. Hari, I. Frosio, T. Tsai, A. Troccoli, S. W. Keckler, S. Garg, and A. Anandkumar
    IEEE IV'21: IEEE Intelligent Vehicles Symposium, 2021

  2. NVBitFI: Dynamic Fault Injection for GPUs
    T. Tsai, S. K. S. Hari, M. B. Sullivan, O. Villa, and S. W. Keckler
    DSN'21: IEEE/IFIP International Conference on Dependable Systems and Networks, 2021

  3. Making Convolutions Resilient via Algorithm-Based Error Detection Techniques
    S. K. S. Hari, M. B. Sullivan, T. Tsai, and S. W. Keckler
    to appear in TDSC'21: IEEE Transactions on Dependable and Secure Computing, 2021

  4. Demystifying GPU Reliability: Comparing and Combining Beam Experiments, Fault Simulation, and Profiling
    F. F. do Santos, S. K. S. Hari, P. M. Basso, L. Carro, and P. Rech
    IPDPS'21: IEEE International Parallel & Distributed Processing Symposium, 2021

  5. AV-FUZZER: Finding Safety Violations in Autonomous Driving Systems
    G. Li, Y. Li, S. Jha , T. Tsai, M. B. Sullivan, S. K. S. Hari, Z. T. Kalbarczyk, and R. K. Iyer
    ISSRE'20: IEEE International Conference on Software Reliability Engineering, 2020
    Best Research Paper Award

  6. GPU-TRIDENT: Efficient Modeling of Error Propagation in GPU Programs
    A. R. Anwer, G. Li, K. Pattabiraman, M. B. Sullivan, T. Tsai, and S. K. S. Hari
    SC'20: International Conference for High-Performance Computing, Networking, Storage and Analysis, 2020

  7. GPU Snapshot: Checkpoint Offloading for GPU-Dense Systems
    K. Lee, M. B. Sullivan, S. K. S. Hari, T. Tsai, S. W. Keckler, and M. Erez
    ICS'19: International Conference on Supercomputing, 2019

  8. ML-based Fault Injection for Autonomous Vehicles: A Case for Bayesian Fault Injection
    S. Jha, S. S. Banerjee, T. Tsai, S. K. S. Hari, M. B. Sullivan, Z. T. Kalbarczyk, S. W. Keckler, R. K. Iyer
    DSN'19: IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

  9. Optimizing Software-Directed Instruction Replication for GPU Error Detection
    A. Mahmoud, S. K. S. Hari, M. Sullivan, T. Tsai, and S. Keckler
    SC'18: International Conference for High-Performance Computing, Networking, Storage and Analysis, 2018 (acceptance rate: ~19%)

  10. SwapCodes: Error Codes for Hardware-Software Cooperative GPU Pipeline Error Detection
    M. Sullivan, S. K. S. Hari, B. Zimmer, T. Tsai, and S. Keckler
    MICRO'18: IEEE/ACM International Symposium on Microarchitecture, 2018 (acceptance rate: ~21%)

  11. Modeling Soft Error Propagation in Programs
    G. Li, K. Pattabiraman, S. K. S. Hari, M. Sullivan, and T. Tsai,
    DSN'18: IEEE/IFIP International Conference on Dependable Systems and Networks, 2018 (acceptance rate: ~25%)
    Best Paper Award Runner-Up

  12. Understanding Error Propagation in Deep-Learning Neural Networks (DNN) Accelerators and Applications
    G. Li, S. K. S. Hari, M. Sullivan, T. Tsai, K. Pattabiraman, J. Emer, S. Keckler
    SC'17: International Conference for High-Performance Computing, Networking, Storage and Analysis, 2017 (acceptance rate: ~19%)

  13. SASSIFI: An Architecture-level Fault Injection Tool for GPU Application Resilience Evaluation
    S. K. S. Hari, T. Tsai, M. Stephenson, S. Keckler, J. Emer
    ISPASS'17: IEEE International Symposium on Performance Analysis of Systems and Software, 2017 (acceptance rate: ~30%)

  14. Approxilyzer: Towards A Systematic Framework for Instruction-Level Approximate Computing and its Application to Hardware Resiliency
    R. Venkatagiri, A. Mahmoud, S. K. S. Hari, S. Adve
    MICRO'16: IEEE/ACM International Symposium on Microarchitecture, 2016 (acceptance rate: ~21%)

  15. Flexible Software Profiling of GPU Architectures
    M. Stephenson, S. K. S. Hari, Y. Lee, E. Ebrahimi, D. Johnson, D.Nellans, M. O’Connor, S. W. Keckler
    ISCA'15: International Symposium on Computer Architecture, 2015 (acceptance rate: ~19%)

  16. Locality-Driven Dynamic GPU Cache Bypassing
    C. Li, S. L. Song, H. Dai, A. Sidelnik, S. K. S. Hari, and H. Zhou
    ICS'15: International Conference on Supercomputing, 2015 (acceptance rate: ~25%)

  17. Hardware Fault Recovery for I/O Intensive Applications
    P. Ramachandran, S. K. S. Hari, M. Li, and S. V. Adve
    TACO'14:Transactions on Architecture and Code Optimization, 2014

  18. GangES: Gang Error Simulation for Hardware Resiliency Evaluation
    S. K. S. Hari, R. Venkatagiri, S. V. Adve, and H. Naeimi
    ISCA'14: International Symposium on Computer Architecture, 2014

  19. Relyzer: Application Resiliency Analyzer for Transient Faults
    S. K. S. Hari, S. V. Adve, H. Naeimi, and P. Ramachandran
    TopPicks'13: IEEE Micro, special issue on the Top Picks from the 2012 Computer Architecture Conferences, May - June 2013

  20. Low-cost Program-level Detectors for Reducing Silent Data Corruptions
    S. K. S. Hari, S. V. Adve, and H. Naeimi
    DSN'12: IEEE/IFIP International Conference on Dependable Systems and Networks, 2012 (acceptance rate: ~17%)

  21. Relyzer: Exploiting Application-level Fault Equivalence to Analyze Application Resiliency to Transient Faults
    S. K. S. Hari, S. V. Adve, H. Naeimi, and P. Ramachandran
    ASPLOS '12: International Conference on Architectural Support for Programming Languages and Operating Systems, 2012 (acceptance rate: ~21%)

  22. CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions
    A. Pellegrini, R. Smolinski, L. Chen, X. Fu, S. K. S. Hari, J. Jiang, S. V. Adve, T. Austin, V. Bertacco
    DATE'12: Design, Automation and Test in Europe, 2012

  23. Architectures for Online Error Detection and Recovery in Multicore Processors D. Gizopoulos, M. Psarakis, S. V. Adve, P. Ramachandran, S. K. S. Hari, D. Sorin, A. Meixner, A. Biswas, X. Vera
    DATE'11: Design, Automation and Test in Europe, 2011 (acceptance rate: ~25%)

  24. mSWAT: Low-Cost Hardware Fault Detection and Diagnosis for Multicore Systems
    S. K. S. Hari, M. Li, P. Ramachandran, B. Choi, S. V. Adve
    MICRO'09: IEEE/ACM International Symposium on Microarchitecture, 2009 (acceptance rate: ~24%)

  25. Accurate Microarchitecture-level Fault modeling for Studing Wear-out Faults
    M. Li, P. Ramachandran, U. Karpuzcu, S. K. S. Hari, S. V. Adve
    HPCA'09: Proceeding of the International Conference on High-Performance Computer Architecture, 2009 (acceptance rate: ~19%)

  26. Automatic Constraint Based Test Generation for Behavioral HDL Models
    S. K. S. Hari, V. V. Konda, V. Kamakoti, V. Vedula, K. S. Maneperambil
    TVLSI'08: IEEE Transactions on VLSI Systems in the special section on Design Verification and Validation: Theory and Techniques, 2008

  27. Power Virus Generation Using Behavioural Models of Circuits
    K. Najeeb, V. V. Konda, S. K. S. Hari, V. Kamakoti, V. Vedula
    VTS'07: IEEE VLSI Test Symposium , 2007 (acceptance rate: ~35%)

  28. Constructing Online Testable Circuits using Reversible Logic
    N. Mahammad, S. K. S. Hari, S. Shroff, V. Kamakoti
    VDAT'06: IEEE VLSI Design and Test Symposium, 2006

  29. Efficient Building Blocks for Reversible Sequential Circuit Design
    S. K. S. Hari, S. Shroff, N. Mahammad, V. Kamakoti
    MWSCAS'06: IEEE International Midwest Symposium on Circuits and Systems , 2006


  30. arXiv and Workshop Publications

    Top
  31. Suraksha: A Quantitative AV Safety Evaluation Framework to Analyze Safety Implications of Perception Design Choices
    H. Zhao, S. K. S. Hari, T. Tsai, M. B. Sullivan, S. W. Keckler, and J. Zhao
    SSIV'21: Workshop on Safety and Security of Intelligent Vehicles, 2021


  32. Simulation Driven Design and Test for Safety of AI Based Autonomous Vehicles
    V. Singh, S. K. S. Hari, T. Tsai, M. Pitale
    SAIAD'21: Workshop on Safe Artificial Intelligence for Automated Driving, 2021


  33. Generating and Characterizing Scenarios for Safety Testing of Autonomous Vehicles
    Z. Ghodsi, S. K. S. Hari, I. Frosio, T. Tsai, A. Troccoli, S. W. Keckler, S. Garg, and A. Anandkumar
    arXiv'21
    ART'20: Shorter version accepted at the IEEE International Workshop on Automotive Reliability and Test, 2020

  34. Making Convolutions Resilient via Algorithm-Based Error Detection Techniques
    S. K. S. Hari, M. B. Sullivan, T. Tsai, S. W. Keckler
    arXiv'20

  35. PyTorchFI: A Runtime Perturbation Tool for DNNs
    A. Mahmoud, N. Aggarwal, A. Nobbe, J. R. S. Vicarte, S. V. Adve, C.W. Fletcher, I. Frosio, and S. K. S. Hari
    DSN-S'20: IEEE/IFIP International Conference on Dependable Systems and Networks – Supplemental Volume, 2020, presented at the Workshop on Dependable and Secure Machine Learning (DSML), 2020

  36. Estimating Silent Data Corruption Rates Using a Two-Level Model
    S. K. S. Hari, P. Rech, T. Tsai, M. Stephenson, A. Zulfiqar, M. B. Sullivan, P. Shirvani, P. Racunas, J. Emer, and S. W. Keckler
    arXiv'20

  37. Feature Map Vulnerability Evaluation in CNNs
    A. Mahmoud, S. K. S. Hari, C. Fletcher, S. Adve, C. Sakr, N. Shanbag, P. Molchanov, M. B. Sullivan, T. Tsai, and S. W. Keckler
    SARA'20: Workshop on Secure and Resilient Autonomy (SARA), 2020

  38. HarDNN: Feature Map Vulnerability Evaluation in CNNs
    A. Mahmoud, S. K. S. Hari, C. Fletcher, S. Adve, C. Sakr, N. Shanbag, P. Molchanov, M. B. Sullivan, T. Tsai, and S. W. Keckler
    arXiv'20
    An updated version appeared in in SRC TECHCON'20 with title "HarDNN: Fine-Grained Vulnerability Evaluation and Protection for Convolutional Neural Networks"

  39. Towards analytically evaluating the error resilience of GPU Programs
    A. R. Anwer, G. Li, K. Pattabiraman, S. K. S. Hari, M. B. Sullivan, T. Tsai
    SELSE'19: IEEE Workshop on Silicon Errors in Logic - System Effects, 2019

  40. On the Trend of Resilience for GPU-Dense Systems
    K. Lee, M. B. Sullivan, S. K. S. Hari, T. Tsai, S. W. Keckler, M. Erez
    DSN-S'19: IEEE/IFIP International Conference on Dependable Systems and Networks – Supplemental Volume, 2019, also presented at the IEEE Workshop on Silicon Errors in Logic - System Effects, 2019 and received Best of SELSE Award

  41. Kayotee: A Fault Injection-based System to Assess the Safety and Reliability of Autonomous Vehicles to Faults and Errors
    S. Jha, T. Tsai, S. K. S. Hari, M. Sullivan, Z. Kalbarczyk, S. W. Keckler, and R. Iyer
    ART'18: IEEE International Workshop on Automotive Reliability & Test, 2018

  42. An Analytical Model for Hardened Latch Selection and Exploration
    M. Sullivan, B. Zimmer, S. K. S. Hari, T. Tsai, S. Keckler
    SELSE'16: IEEE Workshop on Silicon Errors in Logic - System Effects, 2016

  43. SASSIFI:Evaluating Resilience of GPU Applications
    S. K. S. Hari, T. Tsai, M. Stephenson, S. W. Keckler, and J. Emer.
    SELSE'15: IEEE Workshop of Silicon Errors in Logic - System Effects (SELSE), 2015

  44. Measuring the Radiation Reliability of SRAM Structures in GPUs Designed for HPC
    P. Rech, L. Carro, N. Wang, T. Tsai, S. K. S. Hari, and S. W. Keckler
    SELSE'14: IEEE Workshop on Silicon Errors in Logic - System Effects , 2014

  45. Relyzer: Application Resiliency Analyzer for Transient Faults
    S. K. S. Hari, H. Naeimi, P. Ramachandran, S. V. Adve
    SELSE'11: IEEE Workshop of Silicon Errors in Logic - System Effects , 2011

  46. Understanding When Symptom Detectors Work by Studying Data-Only Application Values
    P. Ramachandran, S. K. S. Hari, S. V. Adve, H. Naeimi
    SELSE'11: IEEE Workshop of Silicon Errors in Logic - System Effects, 2011.

  47. CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions
    A. Pellegrini, R. Smolinski, X. Fu, L. Chen, S. K. S. Hari, J. Jiang, S. V. Adve, T. Austin, V. Bertacco
    SELSE'11: IEEE Workshop of Silicon Errors in Logic - System Effects, 2011


Patents:

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Software:

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